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Workflows for memory technology development
Early access to metrology and defect analysis data is essential for accelerating the yield ramp and reducing time to market in memory manufacturing. We address these challenges with wafer-level and package and die-level workflows that facilitate process development. These workflows enable development engineers to gain access to critical dimension (CD) data and identification of crucial defects.
Wafer-level memory technology workflows
Accelerating the learning cycles of fab yield necessitates early access to metrology and defect analysis data. By obtaining samples or accessing analytical data directly from the wafers in the fab, metrology and yield enhancement groups can gain valuable insights into the fabrication process at an earlier stage. This, in turn, enables faster process development, yield ramp, and ultimately a quicker time to market. We offer wafer-level workflows of metrology and defect analysis that effectively tackle the challenges associated with the yield learning cycle.
Advanced memory devices undergo complex manufacturing processes. Obtaining metrology and defect analysis information directly from the wafers at an early stage can greatly expedite the generation of actionable data. We provide wafer-level scanning electron microscopy (SEM) metrology, transmission electron microscopy (TEM) metrology, and defect analysis workflows that promote efficient fab yield learning cycles.
Wafer-level SEM metrology
Helios 5 PXL Wafer DualBeam inline SEM metrology workflow
SEM metrology is commonly used for measuring memory cell array CDs in large areas. By combining it with focused ion beam (FIB) milling on wafers, engineers can use SEM metrology to assess site-specific CD variations across wafers, particularly in high-aspect-ratio stacks. The Thermo Scientific Helios 5 PXL PFIB Wafer DualBeam is capable of high-throughput cross-sectional and diagonal milling using a Xe+ plasma ion beam through 3D NAND layers and DRAM capacitors, providing nanometer-scale CD information directly from 300 mm wafers.
Additionally, with the assistance of proprietary gas chemistry, the Helios 5 PXL DualBeam can perform wafer-level, site-specific delayering to measure CDs of the memory cell array at target layers. These workflows enable acquisition of high-resolution SEM metrology data directly in the fab, significantly accelerating the feedback cycle and time to data.
3D NAND memory cell through-stack SEM metrology using diagonal milling on the Helios 5 PXL Wafer DualBeam
By leveraging our comprehensive suite of solutions, advanced memory manufacturers can effectively address the challenges associated with memory device scaling and achieve precise control over critical dimensions in complex structures.
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3D reconstruction of 3D NAND memory cell arrays using Avizo Software
Wafer-level TEM metrology
Wafer-level TEM metrology workflow
TEM metrology plays a crucial role as the "gold standard" reference for all metrology techniques throughout the various stages of memory device fabrication. From process development to yield ramp and high-volume manufacturing, TEM metrology ensures the accuracy and reliability of measurements. It serves as the benchmark against which other metrology techniques are compared, guaranteeing high standards in the industry. With its comprehensive and precise analysis capabilities, TEM metrology plays a vital role in achieving optimal device performance and efficiency.
We offer wafer-level workflow solutions to meet the increasing demand for higher volumes of TEM metrology data in memory device scaling. These solutions encompass sample preparation, imaging and analysis, and TEM metrology, specifically tailored to address the challenges associated with CD control in complex structures like 3D NAND memory cells, DRAM transistors, and capacitors.
The Thermo Scientific Helios 5 EXL Wafer DualBeam prepares TEM samples of superior quality and volume directly from 300 mm wafers. The system incorporates advanced ion beam technology and automation, helping to ensure sample consistency, repeatability, and a high success rate.
Following sample preparation, the Thermo Scientific Metrios 6 (S)TEM, designed to meet the demand for TEM metrology data, enables the imaging and analysis of TEM samples. The Metrios 6 (S)TEM offers automated sample loading, navigation to regions of interest (ROI), and it performs alignment, imaging, and metrology analysis tasks.
TEM metrology analysis on 3D NAND devices.
By leveraging our comprehensive suite of solutions, advanced memory manufacturers can effectively address the challenges associated with memory device scaling and achieve precise control over critical dimensions in complex structures.
Wafer-level defect analysis
Fully automated deep mill workflow for VC defect redetection and SEM root cause analysis
1-click piece extraction for VC defect redetection and TEM root cause analysis
The complexity of memory devices has led to an increase in buried physical defects in high-aspect-ratio structures. To address this issue and improve production yield, it is crucial to conduct root cause analysis on these buried defects.
The Thermo Scientific Helios 5 EXL Wafer DualBeam offers wafer-level defect root cause analysis workflows. These workflows include deep mill and 1-click piece extraction. The deep mill workflow is specifically designed for automated cross-section analysis on tall structures such as 3D NAND. On the other hand, the 1-click piece extraction workflow is suitable for smaller defects found in DRAM or 3D NAND devices. With the 1-click piece extraction workflow, sample chunks containing defects can be directly extracted from the wafer and transferred to the Thermo Scientific Helios 6 HD FIB-SEM for TEM sample preparation. Subsequently, the samples can be further analyzed and imaged using the Thermo Scientific Talos F200E TEM or Spectra Ultra (S)TEM.
By utilizing the Helios 5 EXL Wafer DualBeam, manufacturers can accelerate yield enhancement and achieve higher production yield by effectively identifying and analyzing buried defects in memory devices.
Automated deep mill cross-section analysis on 3D NAND etch channels
Package and die-level memory workflows
Semiconductor labs offer a wide range of capabilities in the field of memory device analysis, utilizing advanced metrology and failure analysis workflows. They perform thorough examinations on both wafer die pieces and packaged devices. By employing these workflows, semiconductor labs enable access to detailed and high-volume metrology and failure analysis results pertaining to critical dimensions (CD) and killer defects within complex memory device structures. This meticulous approach helps with the elimination of critical failures and enhances overall device performance.
In addition to wafer-level analysis, memory manufacturers can benefit from conducting more extensive metrology and failure analysis on memory die samples or packaged die samples. We offer scanning electron microscopy (SEM) metrology, transmission electron microscopy (TEM) metrology, and failure analysis workflows at both the package and die level. These advanced solutions enable memory manufacturers to enhance their production yield and optimize device performance.
Package and die-level SEM metrology
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Automated SEM metrology workflow using the Verios XHR SEM
When a significant amount of SEM metrology data is needed, you have the option to utilize a fleet of Thermo Scientific Verios 5 XHR SEM instruments to achieve high-resolution imaging and metrology.
Following ion beam or mechanical sample preparation, the Verios XHR SEM can autonomously capture images of the memory cells throughout the stack, allowing for a substantial volume of data for metrology analysis. The Verios XHR SEM's exceptional level of automation makes it an excellent choice for integration into automated laboratory workflows.
High-resolution SEM imaging and metrology of 3D NAND cells using the Verios XHR SEM.
Package and die-level TEM metrology
Die-level TEM metrology workflows
TEM metrology, also known as transmission electron microscopy metrology, holds immense significance as the primary reference point for all metrology techniques employed in the different phases of memory device fabrication. Whether it is process development, yield ramp, or high-volume manufacturing, TEM metrology is instrumental in ensuring the precision and dependability of measurements. It serves as the ultimate standard against which other metrology techniques are evaluated, guaranteeing the utmost quality and excellence in the industry. With its extensive and accurate analysis capabilities, TEM metrology plays a pivotal role in achieving optimal device performance and efficiency.
We provide comprehensive package and die-level workflow solutions to meet the growing need for higher volumes of TEM metrology data in memory device scaling. Our solutions cover sample preparation, imaging and analysis, and TEM metrology, specifically designed to tackle the challenges related to CD control in complex structures such as 3D NAND memory cells, DRAM transistors, and capacitors.
Our Helios 6 HD FIB-SEM delivers superior quality and volume TEM samples from wafer die samples. This instrument offers the ideal combination of productivity and precision required for memory TEM sample preparation. It leverages the latest advancements in ion beam technology and high-level automation to ensure optimal results.
After sample preparation, our Metrios 6 (S)TEM, designed to meet the demand for TEM metrology data, enables the imaging and analysis of TEM samples.
The Metrios 6 (S)TEM offers automated sample loading, navigation to regions of interest (ROI), and it performs alignment, imaging, and metrology analysis tasks.
With our comprehensive suite of solutions, advanced memory manufacturers can effectively address the challenges associated with memory device scaling and achieve precise control over critical dimensions in complex structures.
TEM EDS metrology analysis on DRAM devices
Package and die-level failure analysis
EFA to PFA workflow for memory device failure analysis
As the complexity of 3D NAND and DRAM devices continues to grow, memory manufacturers are increasingly relying on comprehensive solutions for electrical failure analysis (EFA) and physical failure analysis (PFA). These solutions play a crucial role in identifying and analyzing the root causes of failures in memory devices.
We offer comprehensive EFA to PFA workflows, encompassing fault localization, sample preparation, and imaging and analysis solutions. Our range of products enables efficient failure root cause analysis during memory device fabrication.
The Thermo Scientific ELITE System utilizes the lock-in thermography technique to accurately and non-destructively localize faults in packages, bare die, or wafers. For even higher resolution fault localization, our Thermo Scientific Meridian S System provides optical fault localization capabilities.
To prepare a planar surface for subsequent nanoprobing, the Thermo Scientific Helios 5 PFIB DualBeam and Helios 5 Hydra DualBeam instruments offer the ability to perform large-area cross-sectioning or uniform delayering at the fault location. Finally, our Thermo Scientific nProber IV and Hyperion II Systems excel at pinpointing fault locations in memory devices, such as wordline to wordline shorts, memory cell faults, and peripheral logic transistor defects.
Following the EFA process, memory manufacturers can leverage the innovative Thermo Scientific Helios 6 HD FIB-SEM to efficiently conduct TEM sample preparation with extremely high quality and productivity. By utilizing either the Talos or Spectra (S)TEM, the intricate microstructure of the memory device failure can be observed at atomic-level resolution, thereby offering trusted, ground-truth insights into the root cause of the failure.
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